Some errors I encountered during the development with Cadence tools. Will be updated if I encounter new problems.
NCLaunch doens’t find the Verilog descriptions of standard cells (AND2, INVERT, XOR2, …) after synthesis
After running the synthesis the logic description is translated into the available standard cells provided by the manufacturer. If the NCLaunch compilation of the Verilog output fails, claiming it coudn’t find the modules for standard cells (like AND2, DFFR, OAI21 and so on), it is probably because NClaunch doens’t know where the descriptions for these cells are. The solution is to include them into the
cds.lib file1, in my case it is:
DEFINE cmos8rf_lib /usr/ibm_lib/cmos8_relDM/ibm_cmos8rf/std_cell/relDM/verilog/cmos8rf_lib
After that it should work fine.
Timescale derective missing
When you get the error
Timescale directive missing on one or more modules when running the elaborator to start a simulation, well, you have to give it some timescale. You can give this option in NCLaunch by selecting »Tools« → »Elaborator« and in the new window add at »Other options« the following:
-timescale 1ns/1ns -override_timescale
If you need other timescale values, feel free to adjust.
How to include the timing information in a SDF file into VHDL testbench?
I have a project in Verilog as an output of the place and route process. My testbench on the other hand is written in VHDL, so how do I include the timing information, which is another output of the place and route, into my testbench?
First, compile the SDF file, using
ncsdfc. I’m doing that from the NCLaunch window by double-clicking on it2. After that I have a
project.sdf.X file, the latter being the compiled version.
To include this into your simulation, you need to annotate it. For Verilog you would use a command3, for VHDL you need a command file. An example would be this:
// SDF command file sdf_file COMPILED_SDF_FILE = "project.sdf.X", SCOPE = :inst_TOP, MTM_CONTROL = "TYPICAL", SCALE_FACTORS = "1.0:1.0:1.0", SCALE_TYPE = "FROM_MTM";
The scope you have to give is the instance, the SDF is generated for, starting at the top level instance of your code. In my case my top level is instantiated with »
inst_TOP« in the testbench.
You can load this configuration file in the advanced settings of the elaborator (Menu → Tools → Advanced Options → Elaborator … → Annotation) and then run the elaborator on your testbench.